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Thus the RGB LED will cycle through all possible combinations of colors. I use the 3 MSB’s of the counter to blink the red, green and blue color channel of the RGB LED respectively. Gowin_OSC_div96 Gowin_OSC_div96_inst (.oscout(clk_2M5)) įinally one of the generated clocks can be used to drive a counter, which will get the RGB LED blinking. Alternatively the respective device primtive can be instantiated explicitly.
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To make use of the integrated oscillator another IP core is generated with the IP Generator tool. However, the 24 MHz reference clock can also be used to drive logic directly, without using the PLL. For the start, the PLL is generated by using the IP Generator tool to get the correct parameters for the PLL. The external 24 MHz clock reference should be used in conjunction with the PLL inside the FPGA, in order to generate an adequate clock signal to drive the logic on the FPGA fabric. The Tang Nano offers 2 different clock sources: an on-board 24 MHz oscillator and an integrated oscillator running at roughly 240 MHz. To test that the Tang Nano board is working properly I implemented the infamous blinky LED example. The FPGA configuration bitstream can be programmed into embedded flash memory, into external flash memory or can be written directly to the (volatile) SRAM cells of the FPGA. GOWIN FPGA Designer also comes with a programmer utility which can be used to program the Tang Nano and read out some device IDs and status registers.
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Timing analysis and power analysis reports can be generated once implementation is complete. The PAR step is simple yet effective as well, however I did not test (yet) how PAR performs once the device utilization reaches a higher percentage. In the following GowinSynthesis is assumed to be the selected synthesis engine. I strongly doubt that anyone will use Synplify Pro for GOWIN FPGA’s. The synthesis tool can be set to either GowinSynthesis (included with GOWIN FPGA Designer) or Synplify Pro (external synthesis tool by Synopsys). The design flow is very simple and offers just the most basic options. GOWIN FPGA Designer IDE: home screen, project view, report view and IP generator
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The ToolchainĪll steps from HDL to bitstream are handled by GOWIN FPGA Designer, a graphical IDE which offers a project based design flow. Almost all user IO pins are utilized by the LCD interface if it is used, so there are not many pins left which could be used to get a video signal into the FPGA anymore.
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Regarding the LCD interface I am unsure how this would be useful, except for generating some fancy test patterns. Like most of Sipeed’s latest development boards the Tang Nano comes with a USB-C connector, thus a USB-C cable is required to use the board without unnecessary tinkering. costs just about 5 $ (like the Longan Nano).4 pin JTAG header (split into 2 x 2 pins left/right of the USB-C connector).USB- JTAG downloader/debugger (via USB-C connector).The Tang Nano offers the following features: The GW1N-1-LV is the smallest member of GOWINs “Little Bee” series, which consists of small footprint instant-on FPGA devices for IoT and interfacing solutions. GOWIN is another Chinese chip manufacturer entering the FPGA arena, like Efinix and Anlogic. The Tang Nano is a very very low cost FPGA development board by Sipeed featuring a GW1N-1-LV FPGA produced by GOWIN Semiconductors.